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Hello from Semicon Europa 2012 in
Dresden! The second day of the conference was also extraordinarily interesting. I decided to concentrate on attending
presentations at the Tech Arena of Messe Dresden related to chip scaling. Tech Arena is a classroom setting where
presenters introduce new technologies.
Soltec,
is a major semiconductor company, presented their vision of the future by
introducing a new version of the so-called fully-depleted devices. The presenter
introduced the background as follows:
We have been successful in scaling
down transistors. Every 18-24 months we have been doubling the number of
transistors in a chip (Moore's Law). This feast is stalling now. We have
reached almost the limit at which lithography can be used in the normal way. We
have not yet been able to develop the extreme ultra-violet (EUV) technology that
the industry has been waiting for years for.
Do you remember Deep Blue? This is the IBM supercomputer (almost 1.5 tons in
weight!) that back in 1997 defeated Garry Kasparov in several chess games. Deep
Blue had a computing power of almost 12 GFLOPS (Giga Flops, or 12x109 floating-point
calculations per second).
Nowadays, if you have an iPhone 4S you have in your hands a "computer"
with 16 GFLOPS! The IBM Watson
supercomputer that defeated one of the best Jeopardy players ever has 15 TB of
memory and almost 3,000 processors with a total computing power of 10 TFLOPS!
(10 Tera Flops, or 12x1012 floating-point calculations
per second).
How can we in 10 or 15 years from now
achieve the same computing power in a hand-held device, such as a smartphone? Well,
by scaling. Scaling implies reducing the size of transistors (cost reduction)
and improving their performance (lower the power consumption). We have been
doing this for many years for every new generation of devices (Moore's Law),
until we reached the node size of 28 nm (the smallest feature in a transistor,
normally the Gate).
There are many techniques that the industry has developed
to overcome the fact that our lithography systems can't be used for nodes
smaller than 30 nm. Some of these techniques include EUV (still delayed),
immersion lithography, and double pattering where instead of using one
lithography step we use two steps for the same process.
The latest technologies and the two
that - for now - have been successful are:
1. Fully-Depleted Technology. In this technology the devices (transistors) are built on
top of a very thin layer of buried silicon oxide (known as the BOX). Because the silicon oxide is an insulator, the
technique is knows as fully-depleted silicon on insulator (FD-DOI). The
transistor is fully depleted because there are no carriers in the channel. The
channel is fully depleted, we say. The
following figure depicts a schematic of a MOS transistor (picture taken from http://ece.wpi.edu/courses/ee3901/2005a/SOI_CMOS.pdf )
Without going into the technical details, we know that a
FD-SOI transistor provides much better performance, lower power consumption, and
a footprint (size) that is smaller than transistors built. The fully depleted
transistor channel is simply a space (totally depleted of carriers) that is
defined by its physical dimensions. In fact, the dimension of the channel is
the most important characteristic of these transistors.
Because the channel is totally depleted of carriers there is less variability
from transistor to transistor in the same chip. Channel doping is the main
source of variability in transistors, because it is not possible to dope all
the transistor channels at the same level. Also, a depleted channel increases
the mobility of electrons through the channel when the transistor is in the ON
condition. Finally, a thin, depleted channel allows shortening the length of
the gate. All these benefits translate into making the transistors smaller. It
is expected that this technique can scale at least until 2020. After this date
we will be well into nanotechnology.
2. 3D Integration.
This technique, invented by Intel, is a new type of packaging that stacks
layers of planar devices in three-dimensional arrays. The connection between layers
uses a new technique called through-silicon via (TSV). This technique is especially
important to increase speed of memory devices, to scale memory chips, and to
reduce their power consumption.
Besides memory devices, 3D integration is very useful for the integration in
the same chip of diverse types of devices such microprocessors together with sensors.
A diagram of 3D integration by TSV is as follows: (taken from http://www.mstonline.de/news/pdf/MNI_Broschuere.pdf )
Editor's Note: Click to read Notes from Semicon Europa - Part 1 about Abe's first day in Germany. You can also read Notes from Semicon Europa - Thin Films & Graphene - Part 2. Stay tuned for additional blog entries from Semicon Europa!
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