The idea is that during logic 1 state and logic 0 state of the clock pulse difference circuits will be established.

There is a bridge rectifier that makes the AC into DC. Then when the clock generator gives logic 1, the capacitors charge in one branch, while they discharge (in series) in another branch, giving output. The opposite happens when the clock generator is logic 0. What sort of waveform would be produced at the output?
The lines in red are shown for the pulse generator (clock) giving logic 1 signals, all the NMOS are switched on. The blue lines are for the circuit made when clock gives logic 0, all the PMOS are switched on.


If we used a voltage sensing for switching the branch, instead of a clock generator making them switch at same time gaps, would this be a way to get constant DC from any variable waveform?
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