Analog Composite Sync Converter

combine and use a nand gate at the start .....{2 input one}

Hi Sparky,

The circuit combines the vertical and horizontal synchro signals. The R-C have a large time constant with respect to both the 64usec period for H and the milisecs V signal, so the pin on which there is a capacitor, practically, you have a logic "1". Thus, the input xor's (H and V) are just inverting the signals. The third xor combines the H and V, output pulses having the same duration as the input ones (e.g. 5usec up, 59usec low). The V signal is present at the length of the V sync (1.6msec, I think). During the up period of the V signal, the H signals are present at the same rate of 64usec but with polarity reversed, i.e. the V signal is high for 1.6 msec, but each 64 usec the V signal goes low for 5 usec.

The fourth xor has no functional justification, the fan out of the third is the same. The two transistors form a buffer, so the signal is about 3V across the two 47 ohm resistors (therefore some 1.5V directed to next circuit or 0.75V on a 75 ohm load). On paper, for any H of V signal high you get a 1.5V high at the output. Remember what we saw for the H sync during the V sync signal. If the practical circuit is not working for you, check the connections.

I think I agree with indel here: basically I think the 22 µf capacitors are much too large for this application.

I don' know any thing about TV sync. signals but you said:

The output (composite) should only be high when both H and V are high.

Are you sure?

The way the circuit is designed the output will be high (about 2.5V through 75Ω) any time the Vsync and Hsync signals are stable (not changing), and, will pulse low (0V through 100Ω) when either of them changes.

You may need an additional RC between pins 8 and 12 to prevent double pulses (one at each edge) for input pulses.

Also If the output signal is the wrong way up: think of the last XOR as a programmable buffer: it's a non inverting buffer with the spare (pin 13) input pulled low as shown, and, an inverting buffer if you pull the spare input high.

The RC needs to be big, because there purpose is to detect the "idle" state of the sync signal, so we can tell when they are in their "active" state. VGA has both active high and active low sync states depending on resolution.

As to having the output sync low for the whole period of the vertical sync, (which seems to be what you say you want), you DON'T want to do that, that will cause the monitor to lose horizontal sync during the vertical retrace period. TV standard require "inverted" horizontal syncs during the vertical sync period to keep the horizonal section from losing sync.