Frequency Detector

Hi,

What happens is that the frequency is measure by a counter and the Phase is base on a window area reference to the VCO.

I hope this helps.

Have you looked at http://en.wikipedia.org/wiki/PLL ?

Look at the data sheet for the 74HC4046. It contains 3 separate phase detectors, one of which is a combination frequency-phase detector, the best one to use to assure lock. Beware: Because of the nature of the phase detector, the basic PPL system is aleady first order from a control standpoint. That is the reason why you will see a second order control loop used, typically based upon a small capacitor in parallel with an RC network. The Philips data sheet for the part gives a good design example.

The pll acts a very important role in the most electronic equipment, especially in communication facility. We should be able use it in our circuits. Its math expression can be derived as follow:

(I forget most of it…, but let me try to do it… if there would be any thing wrong pls point out)

First of all, we assign input signal to Vi = V1*sin(ω1*t+θ1); the signal applies to multiplier, which is the important part of identify phase, is

Vs = V2*cos(ω2*t+θ2);

Set Vm = V1*V2*k1; where k1=coefficient of multiplier. And Vm is its output.

So, we get Vm = k1*V1*V2* sin(ω1*t+θ1) *cos(ω2*t+θ2);

Let k = k1*V1*V2; and change multiplication into sum by trigonometric function formula, we have

Vm = k* 1/2* [sin(ω1*t+θ1+ω2*t+θ2) + sin(ω1*t+θ1- ω2*t- θ2)];

Afterward we have a filter in loop circuit, so the front part of above formula can be cut down. Then we get

Vm = k* 1/2* [sin(ω1*t+θ1- ω2*t- θ2)];

From this we can rewrite as

Vm = k* 1/2* [sin(φ1-φ2)]; where φ1=ω1*t+θ1; φ2=ω2*t+θ2;

At the part of VCO, we have ω2 =k2*Vm+ω0;

Integral to time t, we have;

ω2*t =integral (k2*Vm) +ω0*t;

ω2*t - ω0*t = (k2*Vm)/S =φ2 ;

we have k3/(1+F(s)) for filter node;

finally we get

φ1/φ2 = K* [sin(φ1-φ2)]* (Vm)/S* 1/(1+F(s))

where K=k*1/2*k2*k3;

Now, we see, if the filter =1/(1+Ts),

The equation belong to 1 type system, when step signal applies to it,

We have error φ1-φ2= constant. That means there is a constant different between the two signals. The phase has been locked.

That's all.

It's the simplified situation.

and if I have a 2nd order PLL, in which there are 2 different blocks for phase and frequency?

thanks of all, you are helping me

And if I have a 2nd order PLL, with one block for the frequency and one for the phase?

Thanks, you are helping me.

Your statements:

Set Vm = V1*V2*k1; where k1=coefficient of multiplier. And Vm is its output.

So, we get Vm = k1*V1*V2* sin(ω1*t+θ1) *cos(ω2*t+θ2);

don't follow from Vi = V1*sin(ω1*t+θ1) and Vs = V2*cos(ω2*t+θ2).

Should you have said "Set Vm = Vi*Vs*k1" , or what?

v

Thank you very much, John. Its really me to make a evident mistake.

The formula should be:

"Set Vm = Vi*Vs*k1"

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To: Barbera,

Most of pll chip has two loop circuits, one is for frequency lock at first and another is for phase lock at second. The aim is at speed up phase lock. You can refer to booklet of the chip for your use in practice, as said by post #2 Berniek.

There are too lots of kinds of pll on the market. Some are analogy and others are digital, however their basic principle is same.

The filter, I metioned above is based on one order filter, we can also call it inertia node. Means just a resistor and a capacitor. If you use two orders filter, you can get faster lock speed than just one resistor and a capacitor. If you would add a integrator again. You can get a good tracing of ramp response. If you familiar basic auto control theory, you would understand it very easily.

You

can use 4046 and LM567 for your test chip. They are very cheaper.