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Join Date: Nov 2009
Posts: 31

explanation needed for this circuit.

11/29/2009 5:17 AM

http://216.77.188.54/coDataImages/p/Groups/292/292938/folders/243015/1911232Push-PullDriver.JPG

Hi everyone,can anyone please explain to me how the circuit in the above link works?How the mosfet push pull driver works in the circuit?and what is the purpose of putting a capacitor at the gate of the P-channel mosfet.(main concern is to understand how the push pull driver opereate and the purpose of locating the capacitor )

Please explain to me by telling what happen when the input of the gate of the 2 mosfet is high and low. how the output will be the same with the input?

Thanks for your explanation and reply.

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Guru
Engineering Fields - Electrical Engineering - Analog and Digital Circuit Design Engineering Fields - Electromechanical Engineering - Transformers, Motors & Drives, EM Launchers Engineering Fields - Engineering Physics - Applied Electrical, Optical, and Mechanical

Join Date: Jan 2008
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#1

Re: explanation needed for this circuit.

11/29/2009 12:11 PM

Homework?

The output is actually an inversion of the input. A +5V signal at the gate of IRF620 will cause the Output to go to 0V. A 0V signal at the gate of IRF620 will cause the Output to go to the +100V level noted.

The capacitor "level shifts" the gate drive voltage to IRF9540, which needs a 5V pk-pk squarewave going from +95V to +100V.

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Guru
Engineering Fields - Electrical Engineering - New Member

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#2

Re: explanation needed for this circuit.

11/30/2009 5:37 PM

Start from a quiescent situation (the input voltage is 0V), in which the capacitor is charged, the voltage on capacitor being 100V.

When the input rises to 5 V (the amplitude of working state pulses) and stays there, the lower armature of the capacitor will swing from zero volts to +5V. The other armature, which was at 100V will "go up" in voltage. How much? If diode 1N4001 wasn't there, the voltage on that armature would go to 105V (5V + 100V) and, with a time constant of 1ms, would decay to 100V, after some 5ms. Why? because the capacitor discharge a part of its charge through the resistor. For this situation, the lower transistor is saturated. the load end being at 0V.

Now, if the input becomes, again, zero volt the lower transistor is cut-off (the voltage on its gate is 0V). The capacitor lower armature goes to 0V, and the upper armature goes from 100V (the stable situation after 5 ms) to 95V. Because the upper transistor's gate is biased accordingly. upper transistor becomes saturated, and a full 100V are applied on the load. Well, the saturation voltages will reduce some from the swing of voltage on the load, but not much.

What about the diode? What is its role? The frequency of the input signal is 40 KHz. If for the first situation the lower transistor is on, when the input voltage drops to 0V, the upper armature didn't change too much in 12.5 micro sec (half of the signal period). The diode will provide a discharge of the capacitor , so its voltage, when input voltage goes back to zero, is 95V. Now, with only 95V on the gate and 100V on the drain, the upper transistor saturates, and the 100V are applied to the load.

The diode 1N4001 is not the best choice. Its ratings Vreverse=50V, will make it fail after several power turn on (if not even the first time).

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