FPGA Output Misbehavior

With no program, there is not way to configure the outputs, so they float. The solution is to use a part that is hard programmed, rather than programmed at power-up from a prom. An example would be Actel antifuse based devices. These devices can be programmed off board or on board, but, once programmed, they hold their code. So the I/O are good to go at power-up. Most FPGA manufacturers offer a family with this option.

That "High" state may be just the effect of a weak pull-up during configuration, say some 100K to 1Mohm, set for every I/O pin.

If you have a HIGH-DURING-CONFIGURATION (HDC) pin programmed to LOW state after configuration, and place a pull down resistor in some of the other I/Os, you may compare exactly what is going on right at the end of configuration, and may be that all of them will stay at LOW state during configuration.

Regrettably I have not used a Virtex 4 yet, but I suspect that this HIGH state of the I/Os during config is not a real HIGH State, just a very weak High State.

Jaime Soto Figueroa

http://www.matharts.cl/

I also used micro controller 89c52 and others all are have these same problem, intialy all ports are high in state we also did the same pull down process, its a very easier and cheaper one to make or fix a controller output in a require level , it help only at the power up state after that we can change this value through programaticaly.

Thank you for your valuable suggestions.

K.P.Mahalingam,

Electrical engineer,

India.