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tanwm
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Join Date: Jan 2010
Posts: 1

Rise Time and Fall Time Specs for Altera Stratix II I/Os

03/05/2010 2:14 AM

Hi,

Is there any rise time & fall time of general I/Os specs? I can't find it in Altera Stratix II data sheets. Will capacitors connect to VCC of FPGA affect the rise & fall time timing? How is the calculation done?Is there anyway to control the timing?

Can anyone advise? Really appreaciate it.
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Randall
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Join Date: Aug 2005
Location: Hemel Hempstead, UK
Posts: 5826
Good Answers: 322
#1

Re: Rise Time and Fall Time Specs for Altera Stratix II I/Os

03/08/2010 3:28 AM

There is no input restriction (I know there was on some earlier devices).

The output rise fall time are specified:-

As long as the VCC is properly decoupled additional capacitors won't make any difference (don't really understand the question).

You can use "slew rate" control to slow down Output tRISE and tFALL. It's just an on off setting for each output signal.

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