Ok so its not really a riddle but I can't get my head around this. I have traced a known-to-work, commercial, mass produced circuit on a fairly simple 2 IC pcb with one 8051 and one fm "wireless link" transmitter connected via an SPI peripheral on the 8051 (LPC936).
The question is why would they connect the MISO line of the 8051 to the CLK of the slave??? The CLK of the 8051 just drives an LED, which makes some sort of sense to indicate SPI output. There is no data returned from the slave, and the only thing coming out of the master is an very occasional 2 byte command. I've triple by triple checked the circuit and datasheets. MOSI --> slave's data and ~SS to CE, otherwise.
I'm no SPI guru, so is this spec'd in the standard... that MISO will drive a slave's data clock? Or should I assume I have to bitbang out the whole thing in firmware?
The bus is just one to one pin connection; there are internal pull-ups in the 8051. There doesn't seem to be a great mismatch between the timing specs of the 8051 and the slave.
I can provide data sheets, but I hoped that this question is easier to answer... I'm pouring over both myself and can't see any glimmer of clarity. The pins on the 8051 have no other special uses. Why switch pins??? I can't find anything to suggest the pins are swapped on the 8051...
Many thanks for your thoughts.