a problem in Digital Logic

Because Vil and Vih will be above and below the threshold for the inputs of the next stage of logic. You will have no noise margin on the inputs. Any ringing on the power supply or transmission line will cause spikes on the outputs of the next stage of logic because their inputs are too close to the threshold limit. Vsat/Vil for this output should not sink so many input loads that is DC value is above .6 volts. Also when in the opposite state the Vih should be above 3.8 volts. If too many loads are hooked to the output the drop across the 2k pullup resistor will be high enough to keep the output DC steady state below 3.8V. You can probably hook more then 8 but you will lose your noise margin and spikes in a system are very compromising if this signal output is used to trigger a D or JK flip-flop somewhere.

b) What is current we get from each input? (the answer is 0.82 mA but i don't know how and why?)

Lets say stage-1 is giving the output and stage-2 is getting that output as inputs.

Now when stage-1's output transistor is saturated its Vce is assumed as 0.3V

And, Stage-2 has diodes and at the input and have a pullup resistor of 5K connected to 5V. This setup can deliver a current which can be calculated as...

5V-(stage-2 diode drop + Stage-1 transistor's Vce) divided by 5K

= 5-(0.6+0.3)=5-0.9= 4.1V/5K= 0.82mA

Please Let me know how can you go through the rest of the solution...

c) calculate the collector current based on N. ( answer is 2.4+0.82N)
d) what is the maximum of N if we want the trasistor to be still saturated

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How U can connect a capacitor in I/P of a logic Cct. These are DC coupled ones not a Schmitt Trigger

Fan-out and Storage in TTLs is a problem, but the Gates are always operated at saturation.