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How to Ensure State of Latch at Power On

11/10/2018 2:31 PM

I feel rather silly asking, but it's been a long time since I did digital design. I'm making a latch (SR flip flop) with NOR gates, and wonder how I can ensure it comes up in a desired state when powered on. Or is there a better IC to make a latch?

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#1

Re: how to ensure state of latch at power on

11/10/2018 2:49 PM

Search POWER ON RESET (a simple RC circuit).

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#2

Re: how to ensure state of latch at power on

11/10/2018 10:46 PM

This may not be an easy question to answer, since you haven't specified the type of SR flip flop you are using. Is this a 4000 series CMOS device, a 74xx00 series device TTL/CMOS, a cross-coupled inverter pair made from transistors, etc. If you are more specific with the starting conditions, I might be able to give a more specific answer.

Often, a simple capacitor can be added in a direction to hold the set or reset line as the device powers up. This simple fix usually works most of the time, but may not be reliable under all possible power up/down/up conditions. The previous poster's suggestion of a POR circuit (if done correctly) could make a bullet-proof solution. Are you feeling lucky?

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#3

Re: how to ensure state of latch at power on

11/10/2018 11:06 PM

I'm using CMOS 4001 NOR gates, cross-connected. The inputs will have resistors to ground. I'm thinking maybe just a small cap to +12 on one of the inputs will do the job. I'll breadboard it tomorrow and report.

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#4
In reply to #3

Re: how to ensure state of latch at power on

11/11/2018 12:55 PM

The cap will force the logic state for a power-up condition. The problem with this approach is that during a power glitch, the capacitor may not discharge all the way during the glitch and the system will not reset to the correct state. Usually a diode across the resistor that charges the cap will cause the cap to discharge rapidly allowing a good reset. There are still some glitch conditions that may escape this fix, but the diode significantly reduces the possibility. A true PowerOnReset circuit addresses this potential problem. For a memory refresh, I played around with LTspice, simulating the effect and saw a short power glitch cause the system to reset to the wrong state.

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#5

Re: How to Ensure State of Latch at Power On

11/11/2018 1:25 PM

Well, it was too easy. Here's the circuit:

Adding a tiny 1nf cap causes pin 4 to reliably go high when power is applied. 10k pull down resistors. 12v power.

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#6
In reply to #5

Re: How to Ensure State of Latch at Power On

11/11/2018 1:38 PM

As long as your circuit won't start a fire, kill somebody, or cause other significant harm, this circuit will work well. There is a condition where a specific power up-down-up timing will cause this circuit to fail. If this is not a problem for your application, then continue with your current solution. If the condition occurs, and the user can just cycle power to regain control, that is fine. If your circuit must work under all conditions, then more work is needed.

Have fun!

Carl

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#7
In reply to #6

Re: How to Ensure State of Latch at Power On

11/11/2018 2:39 PM

Nah, just a trigger for an ICBM that'll probably never get used.

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