Because each logic gate has a different function (like summing or simply passing a signal through), they are each configured differently when you look at the internal schematic. (also depends on whether you are speaking of CMOS or TTL gates when looking at internal structure).
Additionally, logic gates must "buffer" the inputs...so hooking many of them in parallel does not cause a signal loss. Also, there is a slight time delay every time a signal presented at the gate goes through (propagation delay). Are you after internal structure?