Output Capacitance Of LDO Regulators

Do what it says in the regulator app' notes and you should be fine.

The usual cure for any instability is a 0.01 or 0.1 uF nice and close the regulator output .

Of course insufficient reservoir C at the input can also cause probs.

Once you have that it's just a mater of sprinkling decoupling Cs around the board as required. One per chip is the safe option. Gnd layout is often V important.
If you have a gnd plane it's easy... if it's single sided board, there are 2 schools of thaught either of which works some of the time and doesn't work some of the time.

Either... Do have a nice big gnd 'loop' around the board.
Or ...... Under NO circumstances have a loop and go for a 'star' type layout.
Or some times a bit of each to cope with different signal types..power , analogue, digital.

To put it another way it's a matter of experience and circuit detail.

Del

(PS. I try and avoid Tantalums because they are environmentally hostile and the stuff is mined under awful conditions)

Thanks Del... I don't face any stability problems (I do use LP3961 of National)... I'm just asking in order to avoid any such probability of instability... I use gnd plane and perfectly placed dec caps at several chips... But i.e. National recommends not to use ceramic cap as the output cap of this regulator, e.g. not to use a 33μF cer cap (which has an extremely low ESR anyway), but a 33μF tant cap (with an ESR between 0,2Ω & 5Ω) instead... So far I'm okay... But I wonder whether all those several cer dec caps which follows (placed on several points on the Vout track) may couse any instability problem (although I haven't seen such a problem till now)... I just want to be sure... I'll put it in another way: In this specific example, is it okay to put a cer cap 100nF at the output of the regulator, in parallel with (and close to) the recomended (by the manufacturer) 33μF tant cap (considering that the cer cap 100nF has an extremely low ESR)?????...

Is it okay to put a cer cap 100nF at the output of the regulator?
Yes. I would definitely recommend a small ceramic close as possible to the regulator output... better safe than sorry.

Del

"Yes. I would definitely recommend a small ceramic close as possible to the regulator output"... If you have a tant cap 33μF (with an ESR i.e. 1Ω) connected in parallel with (and close to) a cer cap 100nF (with an ESR i.e. 0,01Ω) then (from the compination of these two caps) you'll have an equivalent cap of ≈33μF with an ESR of ≈0,01Ω... This ESR≈0,01Ω is, apparently, out of the limits of the ESR that are recommended by the manufacturer (which are 0,2Ω≤ESR≤5Ω)... I mean that the output cap (the combination of these two) will have an ESR well below the 0,2Ω... This seems to be a problem... Am I right???...

I don't know why they have a lower limit on ESR unless it's to limit infintie surge current...

The 2 caps in parallel isn't the same as one big fat low ESR 33uF...
e.g Only the high frequency decoupling cap... the 0.1uF has the low ESR and thus it will not have a big inrush current... it is just there to be a low impedance to high frequencies...(& oscillations)
I feel maybe you are getting into overthink....

Del

you'll have an equivalent cap of ≈33μF with an ESR of ≈0,01Ω.
Nope... you've got to remember.. each cap is like a cap in series with it's ESR.... so

You have (0.1uF in series with 0.01Ω) this is then in parallel with the (33uF in series with 1Ω)

Del

Yeap, Del... You are right... I had a second thought on this...

When you have two equal caps connected in parallel you can say that the equivalent cap (the parallel compination) will have twice the capacitance and half the ESR... For example, two 100μF caps with an ESR=1Ω each, connected in parallel, will give an equivalent cap of 200μF caps with ESR=0,5Ω (this results because these two [R & C] branches are indentical, so the voltage potential at midpoints (between R & C) of each branch are the same, so you can "connect" these two midpoints, resulting [R//R] in series with [C//C] which gives R/2 in series with 2C)...

But when you have two unequal caps (i.e. a 100μF cap with ESR=1Ω connected in parallel with a 100nF caps with ESR=0,01Ω) the two branches are unequal so you can't have [R//R] in series with [C//C]... So you can't say that the ESR(total)=0,01Ω... I suspect that the ESR(total) will be less than 1Ω... It's hard to calculate though...

(BTW they have such ESR requirements because of stability issues... So I must be careful... That's why I insisted on this...)

Thanks... You were very helpfull...

No, you do not have problems with the far away capacitors, because:

1,. They were considered in the LDO requirements.

2,. There is usually enough inductance and resistance in your V+ trace, that will act as a lowpass, reducing the instantanious power demand change.

A note on filter capacitors: there is an upper limit on ESR to allow effective shunting of high frequency components. But there is also a lower limit, under which ringing is virtually guaranteed, and instant demands for the same reason may exceed the LDO current capability resulting in short sags. Bigger LDO does not help, as the same scenario plays out, just slower.

Thanks for your comments Leveles... You said: "1,. They were considered in the LDO requirements." Yes, but how many cer dec caps were considered in their requirements???... You said: "2,. There is usually enough inductance and resistance in your V+ trace, that will act as a lowpass, reducing the instantanious power demand change." Yes, but what about the use of a realy wide track or a local plane as the V+ trace (which means really low inductance and resistance)???... Or what if some of these dec caps are really close to the output of the regulator???... So you have to consider the worst case, where you have such a cer dec cap (i.e. 100nF) exactly next to the output of the regulator... And, then, I wonder if such a case can cause instability problems...

As I said, in my application I haven't seen any such problems (in a low scale production of the card)... But when you plan a mass production (very large quantity) you have to be sure that things are not crucial... Otherwise you may meet such problems in some of the cards (i.e. 1 out of 100)... I don't want any risk...

You worry too much. But you are right to think about it now.

So, build 2 - 3 crude PC board with the same ground plane and a rough approximation of power trace. Put a High frequency capable power FET or some such at the end of it with a resistor according the actual current on your board +50% for margin. Equip one board with the best capacitors, next with the others, etc. Drive the FET with a square wave variable generator. Break out the oscilloscope and have fun. You will learn in one afternoon more, than in weeks fretting about it. Then you gain peace of mind. Once done, put them away in a cabinet for comparison, if or when such a question comes back from production. By the way, I did not even meant etched PC board. Just take the sharp knife and carve it out. Small variations do not matter.

Murphy's law favors the prepared.

I suppose that you mean to connect all the dec caps on the the V+ trace (output of the regulator) and then to connect a FET in series with the load resistor at the end of this trace... Then I can switch on & off the FET (via a square wave) and observe the Vout of the regulator (and see if there is any ringing e.t.c.)... Am I right???...

Make sure you de-rate your tants. by at least 50% when using with switching power supplies (both on the inputs and outputs). The fast spikes cause problems. All capacitor manufacturers have a report like this somewhere on their site:

ADMIN: Removed Resource

The linked article was removed because it is no longer on the host site.

----------------- quote ---------------------------

for example using a 35 Volt rated capacitor

on a 12 Volt rail. The effect of voltage derating in steadystate

conditions is well known, but derating has been

empirically shown to reduce the number of failures in

dynamic applications also, as will be demonstrated later

in this paper.

----------------------- end quote ----------------------

Thanks for the link Randall... I know this derating issue and I always use tant caps with operating voltage at least 3 times the voltage which is applied on them...

You got it quite right in your not #13.

Now go ahead, and have fun.