That sequence is changing. The new Allen-Bradley ControlLogix line has scheduled I/O updates, just not scheduled with the program scan. The state/value of an input could change anytime in the program scan. Good reason to stick with the ages old, "best practice" of buffering your I/O.
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TANSTAAFL (If you don't know what that means, Google it - yourself)
Agree 100% - I invariably read into a chunk of memory at start of scan - then often XOR it with a mask (because half the time I don't know which way up the inputs are going to be when I design the logic). Saves hours of changing XICs into XIOs etc.
I do the same kind of thing on the way out.
I put the input & output images (and the XOR masks) in the CIF (Common Interface File (I think?)). I've written a set of routines (VB) using DF1 to read/write the CIF (N7 in M'logix 1000, N9 in most others, as I recall). Means you don't have to stump up the ridiculous sums they ask for RSLINX.
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"Love justice, you who rule the world" - Dante Alighieri
Follow as many of the links at the end of the article as time allows. Beyond that, you will need the manufacturer's literature for the specific model. You might also look up "ladder logic" on Wikipedia. It is implemented in many PLCs, and even if it is not implemented on your make and model, it gives you some insight into how PLCs think.
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