Precharge PFD

First, standard phase detectors (PD) for phased-locked loops (PLL) work well when the input frequencies are virtually the same (excepting the issue of jitter), but are inefficient in achieving lock when the frequencies are far apart. A second type, a phase frequency detector (PFD) includes frequency information, which can improve PLL performance.

Leafing through various papers uncovered with Google Scholar (GS is your friend), I see most implement PFDs with CMOS cascode fet gate structures, quite unlike the flip-flop + gate schemes common for classic PLL circuits. For example at right we show a "non-clocked" PFD circuit. These are "square-signal" detectors, sometimes called sequential-logic or sequential detectors in early papers. The two inverters in each path serve to remove the dead zone, which is very important.

Now as to the word, precharge. This was used in some early papers, and has stuck around a bit. Since prior to an input change the critical nodes are unchanging, they can be said to lie in a precharged state before the transition. This is a natural consequence of the square-wave logic signals and the gate-oriented structure. I found the use of the precharge adjective especially popular in China and Pacific-rim countries, but since those papers are published there, I couldn't access many of them to see what they had to say about it.