IBM Embraces Chip Stacking

As CMOS scaling slows down, IBM researchers are looking for alternatives, and chip stacking and 3D integration seems to be the way of the future. At the recent SEMI Industry Strategy Symposium in Half Moon Bay, CA, IBM fellow Jon Casey told EE Times that traditional systems really are not designed to handle massive amounts of data coming in at high rates. As a result, the technology giant is looking at alternative ways to address that problem and achieve new levels of I/O performance.

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