NAND Flash Memory by CMOS.

Details of Research

₂Ta₂O₉ film, and then 200-nm-thick platinum film were deposited in this order on a p-type Si semiconductor substrate using a pulsed-laser deposition technique. The conditions of impurity doping to the channel area had been adjusted so that the threshold voltage was optimized for a NAND flash memory cell. The gate, source, drain and substrate electrodes were formed using the photolithography. And then, an n-channel FeFET with a metal-ferroelectric-insulator-semiconductor (MFIS) stacked gate structure was obtained (Fig. 1).

An array structure of a Fe-NAND flash memory was assumed to be as shown in Fig. 2, and the appropriate voltage application conditions that enabled the data program, all erase, and readout operations were carefully examined. Threshold voltages of the FeFET were measured after applying program and erase voltage pulses with a variety of pulse widths. The result was that the pulses with high speed of 10 µs and low voltage of 6V worked enough for showing two distinguishable threshold voltages which corresponded to the two different memorized states. The threshold voltages of the FeFET were measured also after applying program and erase disturb voltages which were the voltages inevitably applied on unselected cells at the same time that the selected cells were programmed and erased. As a result, we found out the appropriate voltage application conditions for the unselected cells to avoid memory errors by the program and erase disturbs.

Judging from the extrapolated lines drawn on the threshold-voltage retention curves of the program, erase, and program disturb operations (Fig. 3), this n-channel FeFET was expected to retain the data for as long as ten years. In addition, the threshold voltages did not change significantly even after 100 million voltage pulses of 10 µs and 6 V were applied for both data programming and erasing (Fig. 4), indicating that the FeFET had more program/erase endurance cycles than 100 million times.

In conclusion, we fabricated an n-channel FeFET for use as a memory cell in an Fe-NAND flash memory and demonstrated that the FeFET had more program/erase endurance cycles than 100 million times and less operation voltage than 6 volts. This memory cell is suitable for a high-density, high-capacity nonvolatile memory of 20-nm and 10-nm technology generations, which will not be realized by conventional flash memories.

Fig.1 N-channel type FeFET with an MFIS gate stacked structure.	Fig.2 Assumed memory cell array of Fe-NAND flash memory.

Fig.3 Data retention characteristics of threshold voltages after program, erase and program disturb operations.	Fig.4 Endurance characteristics.

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