Chips with Graphene

hi..

thanks so much for the reply..

GaN is highly suitable for power devices at micro-wave frequencies but i guess they also are to be doped with silicon.

and regarding graphene, unlike silicon, the electrons here move more freely with lesser obstacles (low resistance), the only obstacle the electrons meet are the very boundaries of the material so the electrons travel 100 times faster when compared to silicon. its current carring capacity is more, thermal conductivity is higher too..

In a few words, Maybe.

Graphene comes in three flavors of orientation.

No one has figured out how to grow any one flavor, excluding the others, for a specific use.

Carbon nanotubes are a rolled up graphene. The sheet or tube will have one of the three orientations when it starts growing and will keep this orientation.

So the person who figures out how to grow single orientated graphene bundles or plates could stand to make a fortune. If that is even possible because many are and have been trying.

Brad

i m aware of the benefits of graphene and the new revolution it can create.. only thing i wanna clearify here is its availability and production.. if it turns out to be more than silicon .. then wht else can stop it??

Hello beatenblood,

The production is the issue for availability. When you have to test every piece to use for production the cost is prohibitive. Handling single molecules is tricky. Even when they are long in one or two dimensions.

Of course if 2/3s of the traces on the Die can fail at test then you can work around it.

The graphene sheets could be: temporarily mounted; tested; and cookie cutter processed too embed on other substrates. But until orientation can be constructed a graphene Die will be impractical.

I could be wrong and a simple work-around will be found and used. So far nothing has been published that I'm aware of.

Brad

thanks brad..

i look more into the orientation part of it..

thanks

I looked for my source for that (a Science Mag. peer review article) and have yet to find it. I'll keep digging.

Brad

Have I missed some major technical advance with graphene? The situation (last time I looked) was that for most applications the inability to turn the devices off far outweighed any benefits that might be provided by the high mobility and high saturation velocity.

To my mind, that means that graphene semiconductors are not even at the point where fibre-optic telecommunications were when I started in the field - i.e.

FibreOpticTelecom (then) . . . . Graphene (now - subject to readers' correction)
Loss theoretically possible. > . No theory for low-current off-state
No high-purity fibre . . . . . . = . No consistent manufacturing method
No CW laser. . . . . . . . . . . . = . No good contacting method
Inadequate laser durability = . No gate technology proved reliable
Meets growing requirement > . Interconnect limitations may make semiconductor speed irrelevant

It took* nearly fourteen years from the theoretical demonstration of viability, and nearly nine years from the from the point at which the first of the practical problems for fibre-optics was solved before roll-out started; had they all been solved simultaneously, it would still have been at least five years.

To my mind the theoretical demonstration of a low-current off-state is the equivalent of the low-loss-fibre prediction. Until we see such a prediction, no-one will fire the starting-gun. Indeed (unlike the fibre-optic case), it is not clear that improving semiconductor properties will have a substantial impact on the performance or economics of a volume product (such as digital semiconductors) - so the race may never really start.

*Low loss fibre theoretically possible (Kao & Hocham: STL) 1966
. Fibre purification (Maurer, Keck & Schultz: Corning): 1970
. Hitchin-Stevenage demonstrator (BT & partners): 1977 (subsequent installations start 1979)

hi...

man... never knew bout this comparison..

thanks man..

i dont quite understand bout the low-current off-state ? wht is it bout?? little dumb there

I don't quite know where to start. Apologies therefore: both for oversimplifications and excessive complexities. No apologies, though, for partly eating my words (as I said, it's good to have my negative thoughts confounded).

In present designs of microprocessor, memory, and graphics ICs, most of the logic gates spend most of their time in a static state. Ideally, they would then conduct no current at all. Unfortunately, life isn't quite like that. Essentially, the current in the static state is the current that is conducted by one of the transistors in the gate when that transistor is switched off.

In practice, as you change the Voltage on the control terminal, the mobile charges (=carriers) in a MOSFET change from predominantly negative, via a relatively low mixture of carriers of both signs, to predominantly positive. The reason that a NMOS FET can be turned off is that the conducting terminals are N-type, and the bias of the device is such that positive carriers are largely prevented from flowing into the terminals. This property depends on the relationship between the bandgap of the material and the characteristic thermal energy. For silicon and room temperature, we are looking at values of about 1.12-eV and 25-meV respectively. As a quick rule of thumb, you need at least 250-meV before you can achieve any sort of reasonable isolation.

So there is a fundamental problem that the bandgap of graphene is zero. Essentially, that means that there is no barrier to positive carriers crossing into the terminals of an NMOS transistor. Because of this, the current through the device would pass through a minimum when the number of positive carriers is equal to the number of negative carriers - and then increase again as you move the control into what would normally be the hard-off region. Add to this that the minimum number of mobile carriers in the material increases exponentially with temperature, and you can see why there is a problem turning the devices off.

There are ways around the zero bandgap - a recent demonstration* being the use of discontinuous nano-structures, such as ribbons with non-typical edges. Albeit impractical for device use at the present time, it was the prospect (now the existence) of such structures that maintained interest for prospective semiconductor device use. (Whether it will be relevant to large-scale IC's is a further question - but I am certain that major players in the field are now doing more than just watching).

*Up to this point, the best on/off current ratio that I had seen for room-temperature graphene was 10:1. (As I haven't been directly involved in the field, this one has only just crossed my desk