How Do FPGAs Work?

Do you know what FPGA stands for?

If so then you will need to know how the gates work and the logic truth tables...

Then you will have the basic understanding of what hundreds can do and how they are fitted into one device.

John.

Here are some good places to start learning:

The Wikipedia article on FPGA's: http://en.wikipedia.org/wiki/Fpga

A tutorial on all major types of FPGA's, and how the technology has evolved:

http://www.eecg.toronto.edu/~jayar/pubs/brown/survey.pdf

This is a good place to start, too.

http://www.fpga4fun.com/HowFPGAsWork.html

I recommend the best of the best:

http://www.xilinx.com/

This is the home page of Xilinx Inc of San José CA.

FPGAs allow constructing parallel processes that take place at once, and that is the advantage in comparison to any Von Newman or Harvard machine.

Von Newman or Harvard machines are like the car manufacturing industry in the early days of automobiles, one single master mechanic doing all operations since the reception of the parts to the final assembly of each whole car, I mean that one single processor or CPU must execute all instructions in a inexorable sequence, that may have branches that may be walked along by that single processor.

FPGAs are like modern car makers, where hundreds of workers (or robots) work at once doing one single operation each one, and these workers form a manufacturing process that may or may not coincide in a final step, say the final roll-off of each car to the company parking place, or they may not coincide at all, because they are engaged in the fabrication of different products, say cars and vans.

A simple comparison is the execution of a calibration polynomial in floating point, where the parameters may be altered upon installed semnsors, thus preventing the practical use of a monstrous ROM look-up table, for example, let

Y = X * (X * (X * (X * A4 + A3) + A2) + A1) + A0

Where X is a signal, and Ai are parameters that may be also varying on taken from sensors, or read from a table already freeze inside the program memory.

A Von Neuman or a Harvard machine should process this as a sequence, which after compilation generates the following steps, assuming all variables are already declared:

Sample X

Read A4

Read A3

Read A2

Read A1

Read A0

C4 = X * A4

C43 = C4 +A3

C3 = C43 * X

C32 = C3 + A2

C2 = C32 * X

C21 = C2 + A1

C1 = C21 * X

Y = C1 + A0

Each of this steps takes time for the CPU that must execute all operations as one single worker, thus the maximum frequency of sampling X(t) is limited by the length of the process.

Inside FPGAs, a whole structure using four floating-point multipliers and four floating-point adders can be built as a graph function, as in a car assembly chain, where many different workers are doing the same operation all the time. A clock acts as a schedule manager, assuring that every middle step is finished before using the result for the next step, that is referrer to as synchronous process, and a time counter gives the corresponding "age" to each sample, thus preventing the operation between samples and intermediate results of different birth dates. Sampling rates well above 100 MHz are now typical with FPGAs.

Jaime Soto Figueroa

http://www.matharts.cl/