Push Pull Amplifier Circuit

http://en.wikipedia.org/wiki/Push%E2%80%93pull_output

I don't like this circuit. The capacitor connecting the pull-up FETs gate to the input signal has no discharge path other than the TTL input signal path. This is precisely why the author insists on a minimum 2 kHz input square wave. Any long term 0 input signal will turn both transistors off, thus creating a tri-state like no connection condition. But any long term 1 input signal will turn on the pull down transistor making a 0 output. This maybe precisely what the author intended and work perfectly in the original application. But this high pass inverter design seems like an atypical purpose to me.

Homework alert!