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Anonymous Poster

Least Material Condition (LMC) and Hole Size

12/23/2009 1:55 PM

Hi there.

I have a question about LMC, and I've hit a brick wall with it.

If I have a hole whose dim is 8.45/8.20, and an LMC of 0 is specified in the control box, what would be the most adventageous hole size? I might have the thinking backwards on this one.

Thank you

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#1

Re: Least Material Condition (LMC) and Hole Size

12/23/2009 6:29 PM

LMC=max hole dim.

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#2

Re: Least Material Condition (LMC) and Hole Size

12/23/2009 10:35 PM

The least material condition corresponds to maximum material removed (8.45) and the hole must be perfectly located at that dimension. The smaller the hole, the greater the location tolerance, so 8.20 would give the largest location tolerance.

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Anonymous Poster
#3
In reply to #2

Re: Least Material Condition (LMC) and Hole Size

12/28/2009 7:20 AM

Great

Thank you all very much!!

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#4

Re: Least Material Condition (LMC) and Hole Size

12/28/2009 8:41 AM

Begs the question though....... why tolerance a hole in such a manner? Smaller hole gets MORE locational tolerance? I'm I missing something?

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#5
In reply to #4

Re: Least Material Condition (LMC) and Hole Size

12/28/2009 11:20 AM

Good question! I'd like to know when this application would be used. (I understand if this is a post at least material getting more position tolerance, but a hole...Hmmm)

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Anonymous Poster
#6
In reply to #5

Re: Least Material Condition (LMC) and Hole Size

01/18/2010 2:23 PM

In the reading I've done, it seems to be used mostly in tube applications, where you want to control the thickness of the tube wall.

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#7
In reply to #5

Re: Least Material Condition (LMC) and Hole Size

01/18/2010 2:31 PM

Geometric Dimensioning and Tolerancing.

Background:

http://www.efunda.com/designstandards/gdt/introduction.cfm

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#8

Re: Least Material Condition (LMC) and Hole Size

06/04/2010 2:31 PM

Okay guys,

There's a lot more to LMC than maintaining minimum wall thickness. Think about how an integrated circuit gets mounted on a PC board. If there are solder tails on the IC, they get soldered to pads on the PCB. A proper solder joint requires a proper solder fillet around the tail. Assuming the width of the tail is smaller than the width of the pad on the PDB, the worst condition of size for the two features will be MMC for the solder tail and LMC for the pad, i.e., when the pad is at its smallest and the tail is at its largest there is less "real estate" left over for the solder fillet. So if you take the LMC of the pad and subtract from it the MMC of the tail, you get a difference in widths. From that difference, subtract 2 times the solder fillet requirement, and you are left with the total positional tolerance that you will need to divide up -- equally or unequally (your choice) -- between the pad and the tail. The tail position tolerance gets modified at MMC because that was its worst condition of size. The pad position tolerance gets modified at LMC because that was its worst condition of size. As the tail gets smaller within its limits of size, you get a bonus tolerance, but the edge of the tail will never get closer to the edge of the pad than what is required for the solder fillet. As the pad gets bigger, it too, gets a bonus tolerance, allowing it to move farther from its true position. But again, its edge will never get closer to the edge of the tail that what is required for the solder fillet when both features were at their worst conditions of size...when you calculated the total positional tolerance.

Another place where the LMC principle is applicable is where you need to restrict the placement of an external feature of size. For this example, think of a punch and die. The punch goes through a hole with little clearance. Below it is a larger hole that allows the punched slug to fall out of the die. (And of course, between the two is the stock that you're punching holes in.) Now the worst thing that can ever happen in a punch and die set is for the punch to make contact with the relief hole below it. With the forces exerted by the press, the punch generally lasts one stroke and then is toast. So what is the worst condition of the hole that guides the punch and the worst condition of the relief hole? When the guide hole is at its largest (LMC) its edge is closer to the edge of the relief hole when it is at its smallest (MMC) size. On our assembly drawing, we will see that the two holes are on the same center line, but what is the allowable variation from that perfect coaxial condition? Take the MMC of the relief hole and subtract from it the LMC of the guide hole. What is left is the total position tolerance. Divide that up as you see fit between the two position tolerances and modify them according to their worst conditions of size -- LMC for the guide hole and MMC for the relief hole.

Of course in either of my examples, you need to define the true positions of the related features with basic dimensions relative to functional datum features, and depending on the type of datum features you're working with -- surfaces or features of size -- there may be a bit more to the determination of tolerance than what I've just presented.

Have a good one, guys.

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