RK4 on FPGA

Hello friends,

I am currently trying an implementation of finding solution of stiff nuclear kinetic equations (ODE) on FPGA using Runge-Kutta 4th order(RK4). I am using VHDL for that. In the architecture for it, I have an entity designed already by some one which does addition,sub,multiplication and division on 32 bit data. I have to use this entity for finding all the terms required in calculating the 4 Ks in RK4 method. So I have designed an entity (which i call sequencer) that sequences all the operations.

Now in architecture for sequencer, I have made one master process that issues commands like read, write to memory and initiates the arithmetic operations. This process in fact communicates with several different processes(you may call them sub-process) using flag bits for proper sequencing of operations (remember that only 2 operands at a time unlike in higher-level languages like C. So for calculating A*B*C, I have to calculate A*B first, store in memory, then use this product to multiply with C.). Each sub-process handles a particular decision of doing an operation based on previous operations, using a signal of type integer. This signal is incremented in the master process and the value of the signal is used by all the processes to keep track of all the previous operations done and also to ensure that no operation is repeated. But the problem is that with this architecture, the program is becoming too lenghty and I fear that the Synthesizer will complain. Can anyone help me out with a better architecture or a better way of communicating between processes?