How Good is Partially TMRed Design

Hello,

I am a FPGA guy and interested in understanding signle event effect on FPGA (especially, Xilinx FPGA). I have two questions:

1) When partially TMRed design is allowed, how do we know how good the design is? Is there any quantitative way to measure the susceptibility of a certain design? I've heard about STARC, but I wonder if it is in academia or available for real work.

2) How do we translate high level requirement such as "less than 1 error per day" to design details such as scrubbing rate, degree of TMR(fully, partially, no TMR)? I guess it should be based on real measurement at expected altitude and device.

If anyone knows, could you answer my questions? Thank you for your help.