EEPROM (AT28C010-12DK-SV) is
having a lock/unlock feature for enable/disable of software write protection.
Under locked condition, data cannot be written to the device. Once locked data
can be written only after unlocking.
EEPROM is locked by following
write sequence.
Data 0xAA to address 0x5555
Data 0x55 to address 0x2AAA
Data 0xA0 to address 0x5555
EEPROM is unlocked by following
write sequence.
Data 0xAA to address 0x5555
Data 0x55 to address 0x2AAA
Data 0x80 to address 0x5555
Data 0xAA to address 0x5555
Data 0x55 to address 0x2AAA
Data 0x20 to address 0x5555
These writes has to be
performed with a gap of <150us (between writes). While doing so none of
these data is physically written to corresponding addresses, instead lock or
unlock will be performed (to perform actual data write, there has to be a delay
of 10ms between writes).
My system name is PE and it has multiple versions built.
In PE FM, the gap between writes
(for lock/unlock sequences) is kept as commandable (multiples of 16us; minimum
is 16us). It is found that lock has happened (while lock command was given).
Subsequently, unlock is not working. Lock/unlock status is verified by
attempting to write a different data to a dummy location.
In PE EM, lock/unlock is
working, but upto 48us gap (between writes) only (against the spec of
<150us). In another EM where MIL-883 EEPROM is wired, it is seen that
lock/unlock works upto 256us delay (meeting the specs). It is felt that the
EEPROMs wired in FM (issued from ISAC) could be marginal in this spec. and may
need gap less than 16us (which cannot be given PE FM).
Proper loading to EEPROM
(before locking) and proper functioning of PE shows that there is no hardware
defect (PCB, FPGA, etc). i.e. all normal read/write with EEPROM is OK. Write
timings in lock/unlock are verified on scope and found OK. This problem is
there with both sections in PE.
So is the problem due to EEPROM out of spec for lock/unlock timings ???
Please Help..