Contact in an Uncertain Future

For years, test engineers have lamented the loss of access to circuit nodes for testing and fault isolation. On devices, the exploding ratio of circuit elements to I/O pins dramatically reduces the ability to examine their internal behavior. On boards, the disappearance of through-hole parts and the proliferation of ball-grid arrays and other devices that hide their logic nodes preclude conventional bed-of-nails testing. How have your test strategies changed to address these limitations? What trade-offs have you made between circuit quality and the time and money costs of test? How do you incorporate conventional methods such as in-circuit test into the mix? How well will your solutions serve as the technology continues to evolve?

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