Have a look at the seminar papers of analog devices (analog.com) about hi-speed-ADC and -DAC;
they have excellent application notes and data sheet informations too.
Good luck ! Uwe
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The sum of intelligence on earth is a constant. And the population grows and grows and .....
That's a big question - so here's an inappropriately small answer. If you have detail about the requirement, then you can start to go deeper into the appropriate areas. Note that small, fast etc. are relative to the technology, so slow techniques are sometimes used in faster products.
Any design work in this area requires some depth of understanding. Sigma-delta converters are regarded as particularly demanding
Slow, high absolute precision: dual slope (used in many meters)
Slightly faster, good signal-to noise: Single-bit sigma-delta
Faster again: good signal-to-noise: multi-bit sigma-delta
Small size, modest power, medium speed, reasonable performance: - SAR
Slightly faster and rather larger than straightforward SAR: pipelined SAR.
You talk about pipelined SAR converters. I am wondering if this might be a scheme I have been thinking about.
An n bit SAR requires n+1 clock cycles to make a conversion if I remember right. If you need conversions faster than the SAR can perform them, why not have multiple SARs, conceptually in parallel. While SAR1 is calculating, you grab the next sample with SAR2, and then a sample with SAR3... ad infinitum. You can then read each sample sequencially on each conversion complete (probably through a MUX). And of course I am talking of complete SAR converters here... not just the registers... and with individual sample and holds for each converter.
Youre right, Bill, thats a good method. A simple solution is taking
2 identical SARs and driving one with an inverted clock - you then
double yout data rate like with DDR.
If you need more channels you have to build clocks with different
phases, but dont make the mistake to do this by FPGA`s - the jitter is
terrible.
regards Uwe
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The sum of intelligence on earth is a constant. And the population grows and grows and .....
There are several pipeline architectures. The ones you describe can work fine, but tend to result in pattern* noise, which can be a problem (depending on your application). What is certain is that multiple monotonic ADCs in this architecture do not necessarily result in a monotonic assemblage. They also take up a fair bit of real estate. This used to be a way of getting additional speed from multiple ADCs where the bandwidth of the S&Hs exceeded the conversion rate by a sufficient margin (depending on the number of bits). Unless you already have such DACs available (virtually for free), it is usually more effective to buy/design the most appropriate (faster) architecture.
The type of pipelined SAR DAC that I had in mind when I wrote this would have broken down into smaller ADCs with related DACs and difference amplifiers for each stage of conversion, with registers and S&Hs between each stage.
Regards
Fyz
*The pattern noise can include timing noise as warned by Uwe, as well as offset noise due to S&H errors and/or comparator and DAC noise
ADC Signals
Re: ADC Signals
