FIFO FPGA implementation

1 MEG x 16 bits? That's large for any FPGA I know of, although admittedly my work is not focused on high density. I would check out Xilinx - they make the largest FPGAs, I believe (someone correct me if necessary).

But, my advice is to use an SRAM, and use an FPGA as a controller to make the SRAM behave like a FIFO. Simply operate the SRAM at twice your data rate, so you can perform both a read and write every data "cycle". Keep track of your in and out data pointers in your FPGA.

I'm a fan of Actel FPGAs, since I design for space, and they have a nice family of radiation tolerant FPGAs. But, they also have free tools, and are easy to design with and use. You will need to get a programmer, like their Silicon Sculptor.

Thanks for your reply and your point is taken. It will be better to implement a FIFO using SRAM in conjunction with a controller. Since I am not good at FPGAs, I will look into if I can interface an MCU to SRAM, most probably operating not more then 0.5 Mhz write operations ( means theoratical throughput of 1 MSPS read+write ). The problem with this approach is the number of connections required ( 20 bit address, 8/16 bit data, 8/16 bit FIFO interface). both operations have to be Asynchronized as well.

If you only need sequential access you can use a counter to drive the address lines to require only a reset and increment line. If you need to set the address to some particular location, you could use counters with a parallel load feature and use shift registers to set up the load value. If you are doing high-speed access you should also use counters with a synchronous clock to eliminate the propagation delay that occurs with ripple counters.

Thanks for ur feedback. i have started designing the FIFO using cacaded 8 bit counters, which apparently should resolve the addressing needs. as similar for FIFO, i would use separate read and write pointers which means I must use tri-state couneters. these counters can be reset by a Flag using last 4 bits of counter. will keep u guys posted on progress:)