I can't remember my logic or how to avoid a race.

Call yor XOR signal A. And invert A and call it NOTA. Now you have two signal. One of them going up when XOR change. You can have an rising edge on A or NOTA. Each signal have an capacitor in series and one resistor to ground. When XOR changes you have one positive pulse in one of these resistors. Connect both resistors (capacitor side, no ground side) to two inputs OR gate. At the gate output you can see one pulse when XOR goes up and one pulse when XOR goes down. Pulse widht is function of R and C. For more exact pulse width use triggers between RC and OR gate. May be useful connect diodes in paralell with resistor to send to ground negative pulses (for protect triggers and OR gate). If you need one drawing send me one mail to eduardoreimundo@arnet.com.ar. I don't know how post images. Good luck !

I think it could bee done easier. If you split the square-wave to one direct (A) and one delayed (B) to each input to an XOR-gate, the output of this gate will bee small positive glitches every time the the input change level. The delaying could simply bee done with a RC-circuit.

Anders

If you are using TTL Logic parts you could use like a 74123. It is a dual retriggerable multivibrator. Since there are two and they have both an inverting and a non-inverting input you can have one trigger on a positive going edge and the other on a negative going edge then OR the outputs to get a single pulse to clock your latches. You use a resistor and capacitor to set the pulse width of the monostable and if you clock on the end of the pulse you can then use the pulse width to set your time delay before latching the inputs.

Merci, mon ami des Etats Unis.

Thank you, I knew that there had to be a simple, elegant solution. You provided not only the change detection but the time delay as well.

My solution would have used the pulse generated by the change detector to trigger a counter that would count off sufficient pulses to allow for any propagation delays and then generate a pulse that would reset the counter for next time and gate the data into an 8 bit latch, this would have required not only the change detector, but a clock generator, a counter, and a circuit to generate the pulse to reset the counter for next time and gate the data into the latches. I am not aware of any advantages to increasing the complexity, part count, space, and power requirements of a design. In my case the difficulty of debugging a circuit must increase with at least the cube of the part count.

I have already printed out the data sheet for the 74123. I need a minimum delay of 70 ns, I think that I will play it safe and go for 100 ns. The changes will not occur so fast that I can't afford to be generous with the delay. For circular indicators I am looking at rotational speeds of as fast as 1 RPS to 1 RPM, in either case a maximum of 256 changes per rotation does not really generate a very short time between transistions when one is already thinking in nano-seconds.

I am surprised that there is not something like a "triple changed gate" in an 14 pin DIP in one of the TTL froup of families. Where O_n would emit a pulse when A_n made either a L->H or an H->L transition. the width, W_n of the pulse would be determined by an external R_n and C_n. The chip would require pins for V_cc, GND, R_n, C_n, A_n, and O_n. Certainly a requirement for change detection must not be unique to my application.

Thanx again - Paul

Pas de problem, de rien. You might also want to look at the 74221, and CMOS parts 4047, 4528, 4538 and one other rather strange device the 4541. Whatever you do, make sure you can still get the part before you design it in.

If I can't find it in the JAMECO catalogue (please excuse the Canadian/British spelling) and I can't download the data sheet I look for a different part.

While I am at it I will ask you a couple of other questions just to betray my total ignorance. How are TTL chips with open collector outputs different and how do you treat them, that was one question in two parts. The second question, suppose that I had a quad 2 input nand chip and I only need two of the four gates, what do I with the unused inputs and outputs on the extra gates?

A personal question, there is one group that I know that will allow words and phrases from a foriegn language slip into their speach, writing, nicknames, etc. They all share a common trait of having spent two years working in that language. If you are one of them send me a private message and I will tell you where I spent my two years and when. If not and you are curious, send me a private message and I will explain it anyway.

Pour la deuxieme fois, merci!

Open collector outputs are just like transistors (in fact they are transistors) and depending on what you are driving you may or may not need to do anything different. If you are, for example driving LED's, then the off state is of no consequence but if you are driving other TTL inputs you should use a pull up resistor. With TTL you should tie unused inputs high for the least amount of current draw but low will also work or pulled up through a resistor. Most of the time they will pull high on their own but good practice is to not count on that. Don't worry about unused outputs, just leave them unconnected. The language thing is nothing more than a fascination with language. I haves studied several but only a couple to any depth.

If you had just needed a simple pulse you could have added one more xor to the end and put a wire to return the out put to one of the inputs. A simple capacitor on the outout would put out a pulse with a pulse width equal to the charge time on the capacitor.

Rbeadle

What you have described will only oscillate. It has no stable state.