There is a PCB, how do you connect these capacitors?

Three capacitors in parallel? In my water based mind (and what I have seen done to resistors) I would roll their ends together and connect them into one set of holes or replace the three with a suitable sized single one.

Analog to water (essentially DC) where a shock wave (signal or noise) takes time to travel a distance the placing of the part may be critical.

At high frequencies my solution might be useless. Can a EE guru please explain it to me in watery terms.

I mean why would a capacitor connected to the 2 ends of a U track be a oscillator?. To my watery mind it is similar to a closed off bypass on a pipeline.

There are two questions here.

1. Where should the capacitors be distributed.
2. Best earthing arrangement.

1. Usually a relatively big reservoir cap' near to the voltage regulator/power suppy, often there is also a small cap too for HF stability (say 0.1uF) . Localised decoupling is usually a 0.1uF on every I.C or say one for every couple of I.Cs, certainly one near any microcontroller/processer/AtoD.

2. Earthing arangement. Obviously a ground plane is best, but in some cost sensitive applications with a single sided board there are two schools of thaught.
a) Have an earth/0v track running in a loop/grid around the board.(A bit like a 'ring main') to maximise the return track area.
b) Have the earth track radiating out from a central point, for controlled return paths.

These are of course generalisations and often both techniques need to be incorporated on the same board to isolate power returns from noisey things like motors or solenoids, or logic from sensitive analogue circuits.
It is all down to experience and expertise.

I always say 'Electronics is easy.... in theory' It is these practical consideration which make it difficult.

Del

(PS Anyone who says you should always use scheme a) or scheme b) or that either of them is always 'wrong' is an idiot.)

Here's my attempt at drawing what I would do with the decoupling capacitor(s) hopefully??!!

I would use whopping big conductors and short capacitor leads to minimise inductance and get the best high frequency decoupling.

Ooooo that picture came out a bit funny!

Better still would be to mount the capacitor on the other side of the board underneath the ic... Right between its power supply legs. Ouch!!

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Thanks for the information.
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Hi cn,

I would do it in the following way:

1. It makes no sense (as in your scetch) to connect a capacitor with one wide trace (e.g. GND) and one small one on the other contact because your ESR values have to be as small as possible to get best filtering results.

2. The smaller CAP has to be as closest as possible to the pin that has to be filtered because it has to conduct the high frequency components and therefore needs to be low inductive/ low resistive. Bigger caps only filter low frequencies - so they may be a little more far away.

3. Putting together numerous capacitors to one value (1µ + 100n + 10n = 1,11µ, so why not take a 1.5µ ?) is no solution because high value caps are bad for high frequency suppression and vice versa, so every cap has its task and should never be omitted or put together. With 3 capacitors in parallel you have three times the capacity but 1/3 of the lead`s inductance and resistance which improves the results dramatically.

4. The proposal shown is for 1-sided PCB. Better would be a doublesided one with a groundplane on GND-potential. Surface mounted devices should be connected with multiple vias per pin because of the same reasons shown in (3). They are always a better choice as they have no leads.

Hope that helps a bit.
Regards Uwe

if C3 connects as this way, how do you think? which is the best way comparing with your pic?

Hi cnpower,

the most critical cap is C2, not C3. Thats because C2 has to reject/filter the high frequencies and C3 has only to buffer. So the connections of the hf-caps have to be as short as possible to get low R and low L. I would prefer the first version as the upper pin of C2 in your sketch is connected with a longer trace which may lead to ringing or worst filter performance.
Regards Uwe

yes, the main role is C2, which is 103 or 104 value. because the C3 has more resistance. its off topic. we are inteersting in their positon.

But most pcb maker recommand the second connection, which is shorter to ground and can cause less interference, because of earthing couple. if there are other more chips after it.

everyone has his reason. I dont know which is more right.

thanks uwe.

I believe it depends on what frequencies your operating at. To a certain extent, it also depends if you're working with analog or digital circuits.

If it's a low frequency, analog circuit (say for an audio circuit), it doesn't matter much where you put the capacitor. You'd have one at the power supply of course (your example 2), but for the ICs, it's not very critical where you put them.

When you get to the higher frequencies (maybe the 100kHz and above) and for digital circuits, it gets a bit trickier. At 100kHz to, say 500kHz, putting them near the ICs is best. Closest to positive rail or negative rail is probably not very critical though.

At even higher ranges, the placement of the capacitor becomes more critical. Thus far, I've seen your example 3 as the most popular (drawing 1 below). The advice I've read about is that it should be as close to the IC as possible and close to the positive rail.

In one extreme example, the capacitor is soldered directly to the positive and ground pins directly (drawing 2 below). I personally happen to like this method. It simplifies the pcb design and I don't have to worry about whether I'm doing the decoupling properly.

If your ICs are socketed there are flat sockets available which have integrated capacitors close to the precision pins. They are a little more expensive but make very good results and you haven`t to do the soldering, either on the back side or on the IC itself. Also SMDs put under the IC directly (if these are through-hole types) are a good solution.
Regards Uwe

We dont take account of frequency here, what we considered is the positon of capacitor at pcb.

if you forget draw the position of the capacitor or you find there is somemore disturbance on the chip , you can use such method (2)to compensate.